Page 140
Epson Research and Development
Vancouver Design Center
TFT FPFRAME Pulse Width Register
REG[03Ch]
RW
LCD
FPFRAME
Polarity
Select
TFT
FPFRAME
Pulse Width
Bit 2
TFT
FPFRAME
Pulse Width
Bit 1
TFT
FPFRAME
Pulse Width
Bit 0
n/a
n/a
n/a
n/a
bit 7
LCD FPFRAME Polarity Select
This bit selects the polarity of FPFRAME for all LCD panels.
When this bit = 1, the FPFRAME pulse is active high for TFT/D-TFD and active low for
passive LCD.
When this bit = 0, the FPFRAME pulse is active low for TFT/D-TFD and active high for
passive LCD.
Table 8-18: LCD FPFRAME Polarity Selection
Passive LCD FPFRAME
LCD FPFRAME Polarity Select
TFT FPFRAME Polarity
Polarity
active high
active low
0
1
active low
active high
bits 2-0
TFT FPFRAME Pulse Width Bits [2:0]
For TFT/D-TFD panel only, these bits specify the pulse width of the FPFRAME output
signal in number of lines.
FPFRAME pulse width in number of lines = (ContentsOfThisRegister) + 1
Note
For TFT/D-TFD only:
(REG[03Ah] bits 5-0 + 1) ≥ (REG[03Bh] + 1) + (REG[03Ch] bits 2-0 + 1)
8.3.7 LCD Display Mode Registers
LCD Display Mode Register
REG[040h]
RW
LCD Bit-per- LCD Bit-per- LCD Bit-per-
LCD Display
Blank
SwivelView™
Enable Bit 1
n/a
n/a
n/a
pixel Select
Bit 2
pixel Select
Bit 1
pixel Select
Bit 0
bit 7
LCD Display Blank
When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are
forced to zero (i.e., the screen is blanked).
When this bit = 0, the LCD display pipeline is enabled.
Note
If a dual panel is used, the Dual Panel Buffer (REG[041h] bit 0) must be disabled (set to
1) before blanking the LCD display.
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
