Epson Research and Development
Page 123
Vancouver Design Center
7.7 MediaPlug Interface Timing
T1
VMPCLK
t2
t2
t2
t2
VMPCLKN
t3
VMPDIN[3:0]
t4
VMPCTRL
t5
t6
VMPLCTRL
t7
VMPDout
Figure 7-54: MediaPlug A.C. Timing
Note
The above timing diagram assumes no load.
Table 7-37: MediaPlug A.C. Timing
Symbol
Parameter
Min
100
0
Max
Units
T1
t2
MediaPlug clock period
VMPCLKN delay from VMPCLK
Input data setup
ns
ns
ns
3
t3
6
t4
VMPCTRL setup
6
Local control signal delay from VMPCLK falling
edge
t5
t6
t7
2
1
ns
ns
ns
Output data delay from VMPCLK falling edge
Output data tristate delay from VMPCLK falling
edge
14
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
