EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
Command
ODTH4
ODT
ODTLon
ODTLoff
tAON (min.)
tAOF (min.)
tAOF (max.)
RTT_Nom
RTT
tAON (max.)
DQS, /DQS
DQ
Dynamic ODT*: Behavior without Write Command; AL = 0, CWL = 5
Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied;
ODT registered low at T5 would also be legal.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
ODTLcnw
ODTLon
Command
ODT
WRS8
ODTH8
ODTLoff
tAON (min.)
tAOF (min.)
tAOF (max.)
RTT_WR
RTT
tADC (max.)
ODTLcwn8
DQS, /DQS
DQ
in
0
in
in
in
in
in
in
6
in
1
2
3
4
5
7
WL
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command
for Duration of 6 Clock Cycles
Note: Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH8 = 6 is exactly satisfied.
Data Sheet E1375E50 (Ver. 5.0)
139
ELPIDA [ ELPIDA MEMORY ]
