EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination
strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by
the “Dynamic ODT” feature as described as follows:
Functional Description:
The Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to ’1’. The function and is described as follows:
• Two RTT values are available: RTT_Nom and RTT_WR.
The value for RTT_Nom is pre-selected via bits A[9,6,2] in MR1
The value for RTT_WR is pre-selected via bits A[10,9] in MR2
• During operation without write commands, the termination is controlled as follows:
Nominal termination strength RTT_Nom is selected.
Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
• When a write command (WRIT, WRITA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is
enabled, the termination is controlled as follows:
A latency ODTLcnw after the write command, termination strength RTT_WR is selected.
A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected
OTF) after the write command, termination strength RTT_Nom is selected.
Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
Table Latencies and Timing Parameters Relevant for Dynamic ODT shows latencies and timing parameters, which
are relevant for the on-die termination control in Dynamic ODT mode:
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a write command is registered by the SDRAM
with ODT high, then ODT must remain high until ODTH4 (BC4) or ODTH8 (BL8) after the write command (see the
figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to
ODT registered low or from the registration of a write command until ODT is registered low.
[Latencies and Timing Parameters Relevant for Dynamic ODT]
Definition for all
Parameters
Symbols
ODTLon
Defined from
Defined to
DDR3 speed bins
Unit
nCK
Registering
external ODT
signal high
ODT turn-on Latency
Turning termination on ODTLon = WL – 2.0
Registering
external ODT
signal low
Registering
external write
command
ODT turn-off Latency
ODTLoff
Turning termination off ODTLoff = WL – 2.0 nCK
Change RTT strength
ODT latency for changing
from RTT_Nom to RTT_WR
ODTLcnw
from RTT_Nom to
RTT_WR
ODTLcnw = WL – 2.0 nCK
ODT latency for change
Registering
Change RTT strength
from RTT_WR to
RTT_Nom
ODTLcwn4 =
nCK
from RTT_WR to RTT_Nom ODTLcwn4 external write
4 + ODTLoff
(BC4)
command
ODT latency for change
Registering
Change RTT strength
from RTT_WR to
RTT_Nom
ODTLcwn8 =
nCK
from RTT_WR to RTT_Nom ODTLcwn8 external write
6 + ODTLoff
(BL8)
command
Minimum ODT high time
registering ODT
ODTH4
ODTH4
ODTH8
tADC
ODT registered low
ODT registered low
ODT registered low
RTT valid
ODTH4 (min.) = 4
ODTH4 (min.) = 4
ODTH8 (min.) = 6
0.3ns to 0.7ns
nCK
nCK
nCK
after ODT assertion
high
Minimum ODT high time
after Write (BC4)
Minimum ODT high time
after Write (BL8)
registering Write
with ODT high
registering Write
with ODT high
ODTLcnw
ODTLcwn
tCK
(avg)
RTT change skew
Data Sheet E1375E50 (Ver. 5.0)
137
ELPIDA [ ELPIDA MEMORY ]
