EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
/CK
ODTLcnw
WRS4
Command
ODTH4
ODT
RTT
ODTLon
ODTLoff
tAON (min.)
tAOF (min.)
tAOF (max.)
tADC (min.)
RTT_Nom
RTT_WR
tADC (max.)
tADC (max.)
ODTLcwn4
DQS, /DQS
DQ
in
in
in
2
in
0
1
3
WL
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command
for a Duration of 6 Clock Cycles, Example for BC4 (via MRS or OTF), AL = 0, CWL = 5.
Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied;
ODT registered low at T5 would also be legal.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK
/CK
ODTLcnw
ODTH4
Command
ODT
WRS4
ODTLon
ODTLoff
tAON (min.)
tAOF (min.)
tAOF (max.)
RTT_WR
RTT
tADC (max.)
ODTLcwn4
DQS, /DQS
DQ
in
0
in
1
in
in
2
3
WL
Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command
for Duration of 4 Clock Cycles
Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH4 = 4 is exactly satisfied.
Data Sheet E1375E50 (Ver. 5.0)
140
ELPIDA [ ELPIDA MEMORY ]
