EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit
If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0, there is also a
transition period around power-down exit, where either synchronous or asynchronous response to a change in ODT
must be expected from the DDR3 SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered
high. tANPD is equal to (WL − 1.0) and is counted backward from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.)
and (ODTLon × tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)).
ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.)
and (ODTLoff × tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)).
See ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period table.
Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows
the three different cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during
the transition period; ODT_A shows a state change of ODT after the transition period with synchronous response.
T1 T3 T5 T7 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 T29 T31 T33 T35
CK
/CK
Command
NOP NOP
CKE
PD exit transition period
tANPD
tXPDLL
ODT_C_async
tAOFPD (max.)
tAOFPD (min.)
DRAM_RTT_C_async
ODT_B_tran
RTT
tAOFPD (min.)
ODTLoff + tAOF (min.)
ODTLoff + tAOF (max.)
tAOFPD (max.)
DRAM_RTT_B_tran
ODT_A_sync
ODTLoff
tAOF (max.)
tAOF (min.)
RTT
DRAM_RTT_A_sync
Asynchronous to Synchronous Transition during Precharge Power-Down (with DLL Frozen) Exit
(CL = 6; AL = CL - 1; CWL = 5; tANPD= WL − 1 = 9)
Data Sheet E1375E50 (Ver. 5.0)
143
ELPIDA [ ELPIDA MEMORY ]
