EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLL-on mode, but DLL is temporarily disabled (i.e. frozen)
in precharge power-down (by MR0 bit A12).
Precharge power-down mode if DLL is disabled during precharge power-down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is not delayed by Additive Latency (AL) relative to the
external ODT command.
In asynchronous ODT mode, the following timing parameters apply (see figure Asynchronous ODT Timings):
tAONPD (min.), (max.), tAOFPD (min.),(max.)
Minimum RTT turn-on time (tAONPD (min.)) is the point in time when the device termination circuit leaves high
impedance state and ODT resistance begins to turn on. Maximum RTT turn-on time (tAONPD (max.)) is the point in
time when the ODT resistance is fully on. tAONPD (min.) and tAONPD (max.) are measured from ODT being
sampled high.
Minimum RTT turn-off time (tAOFPD (min.)) is the point in time when the devices termination circuit starts to turn off
the ODT resistance. Maximum ODT turn-off time (tAOFPD (max.)) is the point in time when the on-die termination
has reached high impedance. tAOFPD (min.) and tAOFPD (max.) are measured from ODT being sampled low.
CK
/CK
CKE
tIH
tIH
tIS
tIS
ODT
tAOFPD (min.)
tAONPD (max.)
RTT
DRAM_RTT
tAONPD (min.)
tAOFPD (max.)
Asynchronous ODT Timings on DDR3 SDRAM with Fast ODT Transition: AL is Ignored
In precharge power-down, ODT receiver remains active, however no read or write command can be issued, as the
respective address/command receivers may be disabled.
[Asynchronous ODT Timing Parameters for All Speed Bins]
Symbol
tAONPD
tAOFPD
Parameters
min.
max.
8.5
Unit
ns
Asynchronous RTT turn-on delay (power-down with DLL frozen) 2
Asynchronous RTT turn-off delay (power-down with DLL frozen) 2
8.5
ns
[ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period]
Description
min.
max.
ODT to RTT turn-on delay
min {ODTLon × tCK + tAON(min.); max {ODTLon × tCK + tAON(max.);
tAONPD(min.) }
tAONPD(max.) }
min { (WL − 2.0) × tCK +
max {(WL − 2.0) × tCK + tAON(max.);
tAONPD(max.) }
tAON(min.);
tAONPD(min.) }
min { ODTLoff × tCK +tAOF(min.); max { ODTLoff × tCK + tAOF(max.);
ODT to RTT turn-off delay
tAOFPD(min.) }
tAOFPD(max.) }
min { (WL − 2.0) × tCK
max {(WL − 2.0) × tCK + tAOF(max.);
tAOFPD(max.) }
+tAOF(min.);
tAOFPD(min.) }
tANPD
WL − 1.0
Data Sheet E1375E50 (Ver. 5.0)
141
ELPIDA [ ELPIDA MEMORY ]
