EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
T0 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 END
CK
/CK
CKE
ODTH4 (min.)
AL = 3
ODT
AL = 3
IntODT
ODTLon = CWL + AL – 2
ODTLoff = CWL + AL – 2
CWL – 2
tAON (max.)
tAOF (max.)
tAOF (min.)
tAON (min.)
RTT
RTT
Synchronous ODT Timing Examples (1): AL=3, CWL = 5;
ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18
CK
/CK
CKE
Command
WRS4
ODTH4
ODTH4
ODTH4
ODT
ODTLoff = WL – 2
ODTLon = WL – 2
ODTLoff = WL – 2
ODTLon = WL – 2
tAON (max.)
tAON (min.)
tAOF (max.)
tAOF (min.)
tAOF (max.)
tAOF (min.)
DRAM_RTT
RTT
RTT
tAON (max.)
tAON (min.)
Synchronous ODT Timing Examples (2)*: BC4, WL = 7
ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BC4) or ODTH8
(BL8) after write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or
from registration of write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied
from ODT registered high at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the
registration of the write command at T7.
Data Sheet E1375E50 (Ver. 5.0)
135
ELPIDA [ ELPIDA MEMORY ]
