EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0 there is a
transition period around power-down entry, where the DDR3 SDRAM may show either synchronous or
asynchronous ODT behavior.
This transition period ends when CKE is first registered low and starts tANPD before that. If there is a Refresh
command in progress while CKE goes low, then the transition period ends tRFC after the refresh command. tANPD
is equal to (WL − 1.0) and is counted (backwards) from the clock cycle where CKE is first registered low.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.)
and (ODTLon × tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)).
ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.)
and (ODTLoff × tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)).
Note that, if AL has a large value, the range where RTT is uncertain becomes quite large.
The figure below shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state
change during the transition period; ODT_C shows a state change after the transition period.
CK
/CK
REF
NOP NOP
Command
CKE
PD entry transition period
tANPD
ODT
tRFC
ODT_A_sync
ODTLoff
tAOF (max.)
tAOF (min.)
RTT
DRAM_RTT_A_sync
ODT_B_tran
ODTLoff + tAOFPD (max.)
tAOFPD (max.)
ODTLoff + tAOFPD (min.)
tAOFPD (min.)
DRAM_RTT_B_tran
ODT_C_async
tAOFPD (max.)
tAOFPD (min.)
RTT
DRAM_RTT_C_async
Synchronous to Asynchronous Transition During Precharge Power-Down (with DLL Frozen) Entry
(AL = 0; CWL = 5; tANPD = WL − 1 = 4)
Data Sheet E1375E50 (Ver. 5.0)
142
ELPIDA [ ELPIDA MEMORY ]
