EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
12.2 Terminating a Burst Read Cycle by Precharge Command
During a burst read cycle without auto precharge, the burst read operation is terminated by a precharge command of
the same banks. When the precharge command is issued at the rising edge of the clock (CLK), the burst read
operation is terminated and the data bus goes to high impedance after the /CAS latency from the precharge
command. The precharge command can be issued after tRAS (MIN.) is satisfied.
Burst length = Full page
T0
T1
T2
T3
T4
T5
CLK
/CLK
CKE
/CAS latency = 2
Command
READ
PRE
Hi-Z
DQ
Q1
Q2
Q3
Q4
/CAS latency = 2.5
READ
Command
PRE
Hi-Z
DQ
Q1
Q2
Q3
Q4
(When tRAS is satisfied)
35
Preliminary Data Sheet E0136E30