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EDD1208ALTA-7A 参数 Datasheet PDF下载

EDD1208ALTA-7A图片预览
型号: EDD1208ALTA-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 128 M位同步DRAM是双倍数据速率( 4 -银行, SSTL_2 ) [128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2)]
分类和应用: 存储内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 78 页 / 1650 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDD1204ALTA, EDD1208ALTA, EDD1216ALTA  
13.5 DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)  
Parameter  
Symbol  
II(L)  
Test condition  
MIN.  
MAX.  
2
Unit Notes  
Input leakage current  
Any input 0 V VIN VDD, all other pins not under  
2  
µA  
test = 0 V  
Output leakage current  
Output high current  
Output low current  
IO(L)  
IOH  
IOL  
DOUT is disabled, VO = 0 to VDDQ + 0.3 V  
VOUT = 1.95 V  
5  
5
µA  
mA  
mA  
–15.2  
15.2  
VOUT = 0.35 V  
13.6 AC Characteristics (Recommended Operating Conditions unless otherwise noted)  
13.6.1 Test Conditions  
Parameter  
Input Reference voltage (Input timing measurement reference level)  
Termination voltage (Output timing measurement reference level)  
High level ac input voltage  
Symbol  
VREF  
MIN.  
MAX.  
Unit Notes  
V
0.49 x VDDQ  
VREF 0.04  
VREF + 0.31  
0.51 x VDDQ  
VREF + 0.04  
VTT  
V
V
1
VIH(ac)  
VIL(ac)  
VID(ac)  
SLEW  
Low level ac input voltage  
VREF 0.31  
V
Input differential voltage (CLK and /CLK)  
Input signal slew rate  
0.7  
1
VDDQ + 0.6  
V
V/ns  
2
Notes 1. Output waveform timing is measured where the output signal crosses through the VTT level.  
2. Slew rate is to be maintained in the VIL (ac) to VIH(ac) range of the input signal swing.  
SLEW = (VIH(ac)-VIL(ac))/ t  
V
TT  
RT = 50Ω  
Output  
CLOAD = 30 pF  
39  
Preliminary Data Sheet E0136E30  
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