EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
11.4 Read to Write Command Interval
To interrupt the burst read operation using the write command, the burst stop command must be issued to avoid
data conflict. The data bus must be high impedance when the write command is issued.
When the write command is issued, any residual data from the burst read cycle must be terminated by the burst
stop command. When /CAS latency is 2, 2.5, the burst stop command must be issued at least 2 cycles prior to the
write command.
T0
T1
T2
T0
T3
T4
T1
T5
T6
T2
T7
T8
T3
T9
T10
T4
T11
T12
T5
T13
T14
Burst length = 8
T6
CLK
/CLK
CKE
/CAS latency = 2
BST
Command
READ A
WRITE B
Hi-Z
Hi-Z
DQS
DQ
QA1
QA2
QA3
QA4
DB1
DB2
DB
/CAS latency = 2.5
Command
READ A
BST
WRITE B
Hi-Z
DQS
DQ
Hi-Z
DB
QA1
QA2
QA3
QA4
DB1
DB2
DQ and DQS : Output
DQ and DQS : Input
33
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
