EDD1208ALTA-7A 参数 Datasheet PDF下载

型号：	EDD1208ALTA-7A
PDF下载：	下载PDF文件查看货源
内容描述：	128 M位同步DRAM是双倍数据速率（ 4 -银行， SSTL_2 ） [128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2)]
分类和应用：	存储内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小：	78 页 / 1650 K
品牌：	ELPIDA [ ELPIDA MEMORY ]

EDD1204ALTA, EDD1208ALTA, EDD1216ALTA

13.4 DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)

Parameter

Symbol

Test condition

/CAS Grade

latency

Maximum

Unit

Notes

x16

t^RC= t^RC(MIN.), t^CK= t^{CK (MIN.)}, One bank,

Active-precharge, DQ, DM and DQS

inputs changing twice per clock cycle,

Address and control inputs changing

once per clock cycle

Operating current

(ACT-PRE)

I^DD0

-7A

-75

-1A

115

100

t^RC= t^RC(MIN.), t^CK= t^{CK (MIN.)}, One

bank, Active-read-precharge,

I^O= 0 mA, Burst length = 2,

Address and control inputs

changing once per clock cycle

Operating current

(ACT-READ-PRE)

I^DD1

CL = 2

-7A

-75

-1A

140

130

150

140

150

140

160

150

170

160

180

170

CL = 2.5 -7A

-75

-1A

CKE ≤ V^IL(MAX.), t^CK= t^CK(MIN.),

All banks idle, Power down mode

Precharge power down

standby current

I^DD2P

CKE ≥ V^IH(MIN.), t^CK= t^CK(MIN.), /CS ≥ V^IH(MIN.),

Idle standby current

I^DD2N

All banks idle, Address and other control inputs

changing once per clock cycle

CKE ≤ V^IL(MAX.), t^CK= t^CK(MIN.), One bank active,

Power down mode

Active power down

standby current

I^DD3P

/CS ≥ V^IH(MIN.), CKE ≥ V^IH(MIN.), t^CK= t^CK(MIN.), t^RC=

t^RAS(MAX.), One bank, Active-precharge, DQ, DM

and DQS inputs changing twice per clock

cycle, Address and other control inputs

changing once per clock cycle

Active standby current

I^DD3N

t^CK= t^CK(MIN.), Continuous burst

read, Burst length = 2, I^O=

0mA, One bank active,

Address and control inputs

changing once per clock cycle

Operating current

(Burst read)

I^DD4R

CL = 2

-7A

-75

-1A

200

170

210

180

195

160

195

160

210

180

220

190

205

170

205

170

250

220

230

200

240

210

225

190

225

190

CL = 2.5 -7A

-75

-1A

t^CK= t^CK(MIN.), Continuous burst

write, Burst length = 2, One

bank active, Address and

control inputs changing once

per clock cycle

Operating current

(Burst write)

I^DD4W

CL = 2

-7A

-75

-1A

CL = 2.5 -7A

-75

-1A

-7A

-75

-1A

t^RFC= t^RFC(MIN.)

CBR (auto) refresh current

Self refresh current

I^DD5

CKE ≤ 0.2 V

I^DD6

Notes 1. I^DD1depends on output loading and cycle rates. Specified values are obtained with the output open.

2. I^DD4Rand I^DD4Wdepend on output loading and cycle rates. Specified values are obtained with the output

open.

Preliminary Data Sheet E0136E30

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