DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 133: I2C_TAR_REG (0x50001304)
Bit
Mode Symbol
Description
Reset
11
R/W
SPECIAL
This bit indicates whether software performs a General Call
0x0
or
START BYTE command.
0: ignore bit 10 GC_OR_START and use IC_TAR normally
1: perform special I2C command as specified in
GC_OR_START
bit
10
R/W
GC_OR_START
If bit 11 (SPECIAL) is set to 1, then this bit indicates whether
a General Call or START byte command is to be performed
by the controller.
0x0
0: General Call Address - after issuing a General Call, only
writes may be performed. Attempting to issue a read com-
mand results in setting bit 6 (TX_ABRT) of the
IC_RAW_INTR_STAT register. The controller remains in
General Call mode until the SPECIAL bit value (bit 11) is
cleared.
1: START BYTE
9:0
R/W
IC_TAR
This is the target address for any master transaction. When
transmitting a General Call, these bits are ignored. To gener-
ate a START BYTE, the CPU needs to write only once into
these bits.
0x55
Note: If the IC_TAR and IC_SAR are the same, loopback
exists but the FIFOs are shared between master and slave,
so full loopback is not feasible. Only one direction loopback
mode is supported (simplex), not duplex. A master cannot
transmit to itself; it can transmit to only a slave
Table 134: I2C_SAR_REG (0x50001308)
Bit
Mode Symbol
Description
Reset
15:10
9:0
-
-
Reserved
0x0
R/W
IC_SAR
The IC_SAR holds the slave address when the I2C is operat- 0x55
ing as a slave. For 7-bit addressing, only IC_SAR[6:0] is
used. This register can be written only when the I2C inter-
face is disabled, which corresponds to the IC_ENABLE reg-
ister being set to 0. Writes at other times have no effect.
Table 135: I2C_DATA_CMD_REG (0x50001310)
Bit
Mode Symbol
Description
Reset
15:9
-
-
Reserved
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
98 of 155
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