DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 140: I2C_INTR_STAT_REG (0x5000132C)
Bit
Mode Symbol
Description
Reset
0x0
2
R
R_RX_FULL
Set when the receive buffer reaches or goes above the
RX_TL threshold in the I2C_RX_TL register. It is automati-
cally cleared by hardware when buffer level goes below the
threshold. If the module is disabled (I2C_ENABLE[0]=0), the
RX FIFO is flushed and held in reset; therefore the RX FIFO
is not full. So this bit is cleared once the I2C_ENABLE bit 0 is
programmed with a 0, regardless of the activity that contin-
ues.
1
0
R
R
R_RX_OVER
Set if the receive buffer is completely filled to 32 and an addi- 0x0
tional byte is received from an external I2C device. The con-
troller acknowledges this, but any data bytes received after
the FIFO is full are lost. If the module is disabled
(I2C_ENABLE[0]=0), this bit keeps its level until the master
or slave state machines go into idle, and when ic_en goes to
0, this interrupt is cleared.
R_RX_UNDER
Set if the processor attempts to read the receive buffer when
it is empty by reading from the IC_DATA_CMD register. If the
module is disabled (I2C_ENABLE[0]=0), this bit keeps its
level until the master or slave state machines go into idle,
and when ic_en goes to 0, this interrupt is cleared.
0x0
Table 141: I2C_INTR_MASK_REG (0x50001330)
Bit
Mode Symbol
Description
Reset
0x0
15:12
11
-
-
Reserved
R/W
M_GEN_CALL
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
0x1
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
M_START_DET
M_STOP_DET
M_ACTIVITY
M_RX_DONE
M_TX_ABRT
M_RD_REQ
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
0x0
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0x1
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
M_TX_EMPTY
M_TX_OVER
M_RX_FULL
M_RX_OVER
M_RX_UNDER
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
These bits mask their corresponding interrupt status bits in
the I2C_INTR_STAT register.
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
102 of 155
© 2014 Dialog Semiconductor
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