DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 120: UART2_SFE_REG (0x50001198)
Bit
Mode Symbol
R/W UART_SHADOW_FI
FO_ENABLE
Description
Reset
0
Shadow FIFO Enable.
0x0
This is a shadow register for the FIFO enable bit (FCR[0]).
This can be used to remove the burden of having to store the
previously written value to the FCR in memory and having to
mask this value so that only the FIFO enable bit gets
updated.This enables/disables the transmit (XMIT) and
receive (RCVR) FIFOs. If this bit is set to zero (disabled)
after being enabled then both the XMIT and RCVR controller
portion of FIFOs are reset.
Table 121: UART2_SRT_REG (0x5000119C)
Bit
Mode Symbol
Description
Reset
0x0
15:2
1:0
-
-
Reserved
R/W
UART_SHADOW_R
CVR_TRIGGER
Shadow RCVR Trigger.
0x0
This is a shadow register for the RCVR trigger bits
(FCR[7:6]). This can be used to remove the burden of having
to store the previously written value to the FCR in memory
and having to mask this value so that only the RCVR trigger
bit gets updated.
This is used to select the trigger level in the receiver FIFO at
which the Received Data Available Interrupt is generated. It
also determines when the dma_rx_req_n signal is asserted
when DMA Mode (FCR[3]) = 1. The following trigger levels
are supported:
00 = 1 character in the FIFO
01 = FIFO ¼ full
10 = FIFO ½ full
11 = FIFO 2 less than full
Table 122: UART2_STET_REG (0x500011A0)
Bit
Mode Symbol
Description
Reset
0x0
15:2
1:0
-
-
Reserved
R/W
UART_SHADOW_TX Shadow TX Empty Trigger.
_EMPTY_TRIGGER This is a shadow register for the TX empty trigger bits
0x0
(FCR[5:4]). This can be used to remove the burden of having
to store the previously written value to the FCR in memory
and having to mask this value so that only the TX empty trig-
ger bit gets updated.
This is used to select the empty threshold level at which the
THRE Interrupts are generated when the mode is active.
The following trigger levels are supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO ¼ full
11 = FIFO ½ full
Table 123: UART2_HTX_REG (0x500011A4)
Bit
Mode Symbol
Description
Reset
15:1
-
-
Reserved
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
94 of 155
© 2014 Dialog Semiconductor
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