DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 92: UART2_LSR_REG (0x50001114)
Bit
Mode Symbol
Description
Reset
3
R
UART_FE
Framing Error bit.
0x0
This is used to indicate the occurrence of a framing error in
the receiver. A framing error occurs when the receiver does
not detect a valid STOP bit in the received data.
In the FIFO mode, since the framing error is associated with
a character received, it is revealed when the character with
the framing error is at the top of the FIFO.
When a framing error occurs, the UART tries to resynchro-
nize. It does this by assuming that the error was due to the
start bit of the next character and then continues receiving
the other bit i.e. data, and/or parity and stop. It should be
noted that the Framing Error (FE) bit (LSR[3]) is set if a
break interrupt has occurred, as indicated by Break Interrupt
(BI) bit (LSR[4]).
0 = no framing error
1 = framing error
Reading the LSR clears the FE bit.
2
R
UART_PE
Parity Error bit.
0x0
This is used to indicate the occurrence of a parity error in the
receiver if the Parity Enable (PEN) bit (LCR[3]) is set.
In the FIFO mode, since the parity error is associated with a
character received, it is revealed when the character with the
parity error arrives at the top of the FIFO.
It should be noted that the Parity Error (PE) bit (LSR[2]) is
set if a break interrupt has occurred, as indicated by Break
Interrupt (BI) bit (LSR[4]).
0 = no parity error
1 = parity error
Reading the LSR clears the PE bit.
1
R
UART_OE
Overrun error bit.
0x0
This is used to indicate the occurrence of an overrun error.
This occurs if a new data character was received before the
previous data was read.
In the non-FIFO mode, the OE bit is set when a new charac-
ter arrives in the receiver before the previous character was
read from the RBR. When this happens, the data in the RBR
is overwritten. In the FIFO mode, an overrun error occurs
when the FIFO is full and a new character arrives at the
receiver. The data in the FIFO is retained and the data in the
receive shift register is lost.
0 = no overrun error
1 = overrun error
Reading the LSR clears the OE bit.
0
R
UART_DR
Data Ready bit.
0x0
This is used to indicate that the receiver contains at least
one character in the RBR or the receiver FIFO.
0 = no data ready
1 = data ready
This bit is cleared when the RBR is read in non-FIFO mode,
or when the receiver FIFO is empty, in FIFO mode.
Table 93: UART2_MSR_REG (0x50001118)
Bit
Mode Symbol
Description
Reset
15:8
-
-
Reserved
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
73 of 155
© 2014 Dialog Semiconductor
DIALOG [ Dialog Semiconductor ]
