DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 92: UART2_LSR_REG (0x50001114)
Bit
Mode Symbol
Description
Reset
7
R
UART_RFE
Receiver FIFO Error bit.
0x0
This bit is only relevant when FIFOs are enabled (FCR[0] set
to one). This is used to indicate if there is at least one parity
error, framing error, or break indication in the FIFO.
0 = no error in RX FIFO
1 = error in RX FIFO
This bit is cleared when the LSR is read and the character
with the error is at the top of the receiver FIFO and there are
no subsequent errors in the FIFO.
6
5
R
R
UART_TEMT
UART_THRE
Transmitter Empty bit.
0x1
0x1
If FIFOs enabled (FCR[0] set to one), this bit is set whenever
the Transmitter Shift Register and the FIFO are both empty.
If FIFOs are disabled, this bit is set whenever the Transmitter
Holding Register and the Transmitter Shift Register are both
empty.
Transmit Holding Register Empty bit.
If THRE mode is disabled (IER[7] set to zero) and regardless
of FIFO's being implemented/enabled or not, this bit indi-
cates that the THR or TX FIFO is empty.
This bit is set whenever data is transferred from the THR or
TX FIFO to the transmitter shift register and no new data has
been written to the THR or TX FIFO. This also causes a
THRE Interrupt to occur, if the THRE Interrupt is enabled. If
both modes are active (IER[7] set to one and FCR[0] set to
one respectively), the functionality is switched to indicate the
transmitter FIFO is full, and no longer controls THRE inter-
rupts, which are then controlled by the FCR[5:4] threshold
setting.
4
R
UART_B1
Break Interrupt bit.
0x0
This is used to indicate the detection of a break sequence on
the serial input data.
If in UART mode (SIR_MODE == Disabled), it is set when-
ever the serial input, sin, is held in a logic '0' state for longer
than the sum of start time + data bits + parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set when-
ever the serial input, sir_in, is continuously pulsed to logic '0'
for longer than the sum of start time + data bits + parity +
stop bits. A break condition on serial input causes one and
only one character, consisting of all zeros, to be received by
the UART.
In the FIFO mode, the character associated with the break
condition is carried through the FIFO and is revealed when
the character is at the top of the FIFO.
Reading the LSR clears the BI bit. In the non-FIFO mode,
the BI indication occurs immediately and persists until the
LSR is read.
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
72 of 155
© 2014 Dialog Semiconductor
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