DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 19: PMU_CTRL_REG (0x50000010)
Bit
Mode Symbol
Description
Reset
11:8
R/W
RETENTION_MODE
Select the retainability of the 4 retention RAM macros.
'1' is retainable, '0' is power gated.
(3) is RETRAM4
0x0
(2) is RETRAM3
(1) is RETRAM2
(0) is RETRAM1
7
6
R/W
R/W
FORCE_BOOST
FORCE_BUCK
Force the DCDC into boost mode at next wakeup.
Setting this bit reduces the deepsleep current.
FORCE_BOOST has highest priority.
When either FORCE_BOOST or FORCE_BUCK have been
written, these bits cannot be changed.
0x0
0x0
Force the DCDC into buck mode at next wakeup.
Setting this bit reduces the deepsleep current.
FORCE_BOOST has highest priority.
When either FORCE_BOOST or FORCE_BUCK have been
written, these bits cannot be changed.
5:4
2
R/W
R/W
R/W
R/W
OTP_COPY_DIV
RADIO_SLEEP
PERIPH_SLEEP
Sets the HCLK division during OTP mirroring
Put the digital part of the radio in powerdown
Put all peripherals (I2C, UART, SPI, ADC) in powerdown
0x0
0x1
0x1
0x0
1
0
RESET_ON_WAKEU Perform a Hardware Reset after waking up. Booter will be
P
started.
Table 20: SYS_CTRL_REG (0x50000012)
Bit
Mode Symbol
Description
Reset
15
W
SW_RESET
Writing a '1' to this bit will reset the device, except for:
0x0
SYS_CTRL_REG
CLK_FREQ_TRIM_REG
...
9
R/W
TIMEOUT_DISABLE
Disables timeout in Power statemachine. By default, the
statemachine continues if after 2 ms the blocks are not
started up. This can be read back from
0x0
ANA_STATUS_REG.
8
7
-
-
Reserved
0x0
0x0
R/W
DEBUGGER_ENABL Enable the debugger. This bit is set by the booter according
E
to the OTP header. If not set, the SWDIO and SW_CLK can
be used as gpio ports.
6
5
R/W
R/W
OTPC_RESET_REQ
PAD_LATCH_EN
Reset request for the OTP controller.
0x0
0x1
Latches the control signals of the pads for state retention in
powerdown mode.
0: Control signals are retained
1: Latch is transparant, pad can be recontrolled
4
3
R/W
R/W
OTP_COPY
Enables OTP to SysRAM copy action after waking up
PD_SYS
0x0
0x0
CLK32_SOURCE
Sets the clock source of the 32 kHz clock
0 = RC-oscillator
1 = 32 kHz crystal oscillator
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
31 of 155
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