DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 17: CLK_RADIO_REG (0x50000008)
Bit
15:8
7
Mode Symbol
Description
Reset
-
-
Reserved
0x0
0x0
0x1
0x0
R/W
R/W
R/W
BLE_ENABLE
BLE_LP_RESET
BLE_DIV
Enable the BLE core clocks
Reset for the BLE LP timer
6
5:4
Division factor for BLE core blocks
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
The programmed frequency should not be lower than 8 MHz
and not faster than the programmed CPU clock frequency.
Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].
3
R/W
-
RFCU_ENABLE
Enable the RF control Unit clock
Reserved
0x0
0x0
0x0
2
-
1:0
R/W
RFCU_DIV
Division factor for RF Control Unit
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
The programmed frequency must be exactly 8 MHz.
Table 18: CLK_CTRL_REG (0x5000000A)
Bit
15:8
7
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R
RUNNING_AT_XTAL
16M
Indicates that the XTAL16M clock is used as clock, and may
not be switched off
0x1
6
5
R
R
RUNNING_AT_RC16
M
Indicates that the RC16M clock is used as clock
0x0
0x0
RUNNING_AT_32K
Indicates that either the RC32k or XTAL32k is being used as
clock
4
3
-
-
Reserved
0x0
0x0
R/W
XTAL16M_SPIKE_FL Disable spikefilter in digital clock
T_DISABLE
2
R/W
XTAL16M_DISABLE
SYS_CLK_SEL
Setting this bit instantaneously disables the 16 MHz crystal
0x0
0x0
oscillator. Also, after sleep/wakeup cycle, the oscillator will
not be enabled. This bit may not be set to '1'when
"RUNNING_AT_XTAL16M is '1' to prevent deadlock. After
resetting this bit, wait for XTAL16_SETTLED or
XTAL16_TRIM_READY to become '1' before switching to
XTAL16 clock source.
1:0
R/W
Selects the clock source.
0x0: XTAL16M (check the XTAL16_SETTLED and
XTAL16_TRIM_READY bits!!)
0x1: RC16M
0x2/0x3: either RC32k or XTAL32k is used
Table 19: PMU_CTRL_REG (0x50000010)
Bit
Mode Symbol
Description
Reset
15:12
-
-
Reserved
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
30 of 155
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