DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 9: OTPC_AHBADR_REG (0x4000800C)
Bit
Mode Symbol
Description
Reset
31:2
R/W
-
OTPC_AHBADR
Tthe AHB address used by the AHB master interface of the
controller (
bits [31:2]).
0x0
1:0
-
Reserved
0x0
Table 10: OTPC_CELADR_REG (0x40008010)
Bit
Mode Symbol
Description
Reset
0x0
31:13
12:0
-
-
Reserved
R/W
OTPC_CELADR
Defines a word address inside the macrocell. Used in modes
AREAD and APROG and is automatically updated.
0x0
Table 11: OTPC_NWORDS_REG (0x40008014)
Bit
Mode Symbol
Description
Reset
0x0
31:13
12:0
-
-
Reserved
R/W
OTPC_NWORDS
The number of words (minus one) for reading/programming
during the AREAD/APROG mode.
0x0
If in APROG mode, and the
OTPC_MODE_PRG_PORT_SEL is enabled (=1), this regis-
ter will not be used and will stay unchanged.
During mirroring, this register reflects the current amount of
data that will be copied. It keeps its value until be written by
the software with a new value. The number of the words that
remaining to be processed by the controller is contained in
the field OTPC_STAT_NWORDS.
Table 12: OTPC_FFPRT_REG (0x40008018)
Bit
Mode Symbol
R/W OTPC_FFPRT
Description
Reset
31:0
Provides access to the fifo through an access port. Write this
register with the corresponding data, when the APROG
mode is selected and the DMA is disabled. Read from this
register the corresponding data, when the AREAD mode is
selected and the DMA is disabled.
0x0
Check OTPC_STAT_FWORDS register for data/space avail-
ability, before accessing the fifo.
Table 13: OTPC_FFRD_REG (0x4000801C)
Bit
Mode Symbol
OTPC_FFRD
Description
Reset
31:0
R
Contains the value read from the fifo, after a read of the
OTPC_FFPRT_REG register.
0x0
Table 14: CLK_AMBA_REG (0x50000000)
Bit
15:8
7
Mode Symbol
Description
Reset
0x0
-
-
Reserved
R/W
-
OTP_ENABLE
-
Clock enable for OTP controller
Reserved
0x0
6
0x0
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
28 of 155
© 2014 Dialog Semiconductor
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