DA14580
FINAL
Bluetooth Low Energy 4.2 SoC
Table 14: CLK_AMBA_REG (0x50000000)
Bit
Mode Symbol
Description
Reset
5:4
R/W
PCLK_DIV
APB interface clock (PCLK). Divider is cascaded with
HCLK_DIV. PCLK is HCLK divided by:
0x0: divide by 1
0x2
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
3:2
1:0
-
-
Reserved
0x0
0x2
R/W
HCLK_DIV
AHB interface and microprocessor clock (HCLK). HCLK is
source clock divided by:
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
Table 15: CLK_FREQ_TRIM_REG (0x50000002)
Bit
Mode Symbol
Description
Reset
0x0
15:11
10:8
-
-
Reserved
R/W
COARSE_ADJ
Xtal frequency course trimming register.
0x0: lowest frequency
0x0
0x7: highest frequencyIncrement or decrement the binary
value with 1. Wait approximately 200 us to allow the adjust-
ment to settle.
7:0
R/W
FINE_ADJ
Xtal frequency fine trimming register.
0x00: lowest frequency
0x0
0xFF: highest frequency
Table 16: CLK_PER_REG (0x50000004)
Bit
15
Mode Symbol
Description
Reset
0x0
R/W
-
QUAD_ENABLE
Enable the Quadrature clock
Reserved
14:12
11
-
0x0
R/W
-
SPI_ENABLE
Enable SPI clock
Reserved
0x0
10
-
0x0
9:8
R/W
SPI_DIV
Division factor for SPI
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
0x0
7
6
5
4
R/W
R/W
R/W
R/W
UART1_ENABLE
UART2_ENABLE
I2C_ENABLE
Enable UART1 clock
0x0
0x0
0x0
0x0
Enable UART2 clock
Enable I2C clock
WAKEUPCT_ENABL
E
Enable Wakeup CaptureTimer clock
3
R/W
-
TMR_ENABLE
Enable TIMER0 and TIMER2 clock
Reserved
0x0
0x0
0x0
2
-
1:0
R/W
TMR_DIV
Division factor for TIMER0
0x0: divide by 1
0x1: divide by 2
0x2: divide by 4
0x3: divide by 8
Datasheet
Revision 3.4
09-Nov-2016
CFR0011-120-01
29 of 155
© 2014 Dialog Semiconductor
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