DM9010
Single Chip Ethernet Controller with General Processor Interface
RO = Read only
WO = Write only
RW = Read/Write
R/C = Read and Clear
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
RW/C1=Read/Write and Cleared by write 1
6.1 Network Control Register (00H)
Bit
Name
Default
Description
7
EXT_PHY
PH0,RW Selects external PHY when set. Selects Internal PHY when clear. This bit will not
be affected after software reset
6
WAKEEN
P0,RW
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
5
4
RESERVED
FCOL
0,RO
Reserved
PHS0,RW Force Collision Mode, used for testing
3
FDX
PHS0,RW Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
2:1
LBK
PHS00,
RW
Loopback Mode
Bit 2 1
0
0
1
1
0
1
0
1
Normal
MAC Internal Loopback
Internal PHY 100M mode digital Loopback
(Reserved)
0
RST
PH0,RW Software reset and auto clear after 10us
6.2 Network Status Register (01H)
Bit
7
Name
SPEED
Default
X,RO
Description
Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
6
5
LINKST
X,RO
P0,
RW/C1
Link Status 0:link failed 1:link OK, when Internal PHY is used
Wakeup Event Status. Clears by read or write 1
This bit will not be affected after software reset
Reserved
TX Packet 2 Complete Status. Clears by read or write 1
Transmit completion of packet index 2
WAKEST
4
3
RESERVED
TX2END
0,RO
PHS0,
RW/C1
PHS0,
RW/C1
2
TX1END
TX Packet 1 Complete status. Clears by read or write 1
Transmit completion of packet index 1
1
0
RXOV
RESERVED
PHS0,RO RX FIFO Overflow
0,RO
Reserved
6.3 TX Control Register (02H)
Bit
Name
Default
Description
7
RESERVED
0,RO
Reserved
Transmit Jabber Disable
6
5
TJDIS
PHS0,RW
PHS0,RW
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
EXCECM
4
3
PAD_DIS2
CRC_DIS2 PHS0,RW
PHS0,RW
PAD Appends Disable for Packet Index 2
CRC Appends Disable for Packet Index 2
Preliminary
17
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
