DM9010
Single Chip Ethernet Controller with General Processor Interface
VID
PID
CHIPR
TCR2
Vendor ID
Product ID
CHIP Revision
TX Control Register 2
28H-29H
2AH-2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
40H
41H
50H
0A46H
9000H
10H
00H
00H
00H
00H
00H
00H
01H
00H
00H
00H
00H
61H
00H
XXH
XXH
00H
XXH
XXH
OCR
Operation Control Register
Special Mode Control Register
Early Transmit Control/Status Register
Transmit Check Sum Control Register
Receive Check Sum Control Status Register
External PHY address
General Purpose Control Register 2
General Purpose Register 2
General Purpose Control Register 3
General Purpose Register 3
Processor Bus Control Register
INT Pin Control Register
Monitor Register 1
Monitor Register 2
System Clock Turn ON Control Register
Resume System Clock Control Register
Memory Data Pre-Fetch Read Command Without Address F0H
Increment Register
SMCR
ETXCSR
TCSCR
RCSCSR
EPADR
GPCR2
GPR2
GPCR3
GPR3
BUSCR
INTCR
MONIR1
MONIR2
SCCR
RSCCR
MRCMDX
51H
MRCMDX1
MRCMD
Memory Data Read Command With Address Increment
Register
Memory Data Read Command With Address Increment
Register
F1H
XXH
XXH
F2H
MRRL
MRRH
MWCMDX
Memory Data Read_ address Register Low Byte
Memory Data Read_ address Register High Byte
Memory Data Write Command Without Address Increment F6H
Register
F4H
F5H
00H
00H
XXH
MWCMD
Memory Data Write Command With Address Increment
Register
F8H
XXH
MWRL
MWRH
TXPLL
TXPLH
ISR
Memory Data Write_ address Register Low Byte
Memory Data Write _ address Register High Byte
TX Packet Length Low Byte Register
TX Packet Length High Byte Register
Interrupt Status Register
FAH
FBH
FCH
FDH
FEH
FFH
00H
00H
XXH
XXH
00H
00H
IMR
Interrupt Mask Register
Key to Default
In the register description that follows, the default column
X
No default value
takes the form:
<Reset Value>, <Access Type>
Where：
<Reset Value>:
1
0
P = power on reset default value
H = hardware reset default value
S = software reset default value
E = default value from EEPROM
T = default value from strap pin
<Access Type>:
Bit set to logic one
Bit set to logic zero
Preliminary
16
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
