DM9010
Single Chip Ethernet Controller with General Processor Interface
Internal regulator 2.5V output for TP TX
35
TXVDD25
P
I
5.7 Miscellaneous
16,17,18, TEST1~TEST4
19
Operation Mode
Test 1, 2, 3, 4 = (1, 1, 0, 0) in normal application
48
TEST5
GP0~6
I,PD Internal system clock source
0: use internal 50MHz clock *(Suggestion)
1: use CLK20MO pin
I/O,PD General I/O Ports
Registers GPCR and GPR can program these pins
The GPIO0 is an output mode, and output data high at default is to power
down internal PHY and other external MII device
GP1~3 defaults are input ports, GP 0,4~6 force to output ports.
O,PD Cable Link Status Output. Active High
68,69,70,
71,
74,75,77
78
LINK_O
This pin is also used as a strap pin to define whether the MII interface is a
reversed MII interface (pulled high) or a normal MII interface (not pulled
high). This pin has a pulled down resistor about 60k ohm internally.
O,PD Issue a wake up signal when wake up event happens
This pin has a pulled down resistor about 60k ohm internally.
79
80
WAKE
PW_RST#
I
Power on Reset
Active low signal to initiate the DM9010
The DM9010 is ready after 5us when this pin deasserted
36
NC
NC NC
5.8 Power Pins
5,20,55,
72,90,73
15,23,42,
58,63,81,
99,76
DVDD
GND
P
P
Digital VDD
Digital GND
5.9 strap pins table
1: pull-high 1K~10K, 0: floating.
Pin No.
Pin Name
Description
57
MDC
Polarity of INT
1: INT pin low active;
0: INT pin high active
DATA Bus Width
65
79
EEDO
WAKE
WAKE
EEDO data width
0
0
1
1
0
1
0
1
16-bit
32-bit
8-bit
reserved
67
EECS
TXD[2:0]
LINK_O
LED Mode
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
IO base address. (not available in 32-bit mode)
IO base = (strap pin value of TXD [2:0]) * 10H + 300H
Reverse MII
52,51,
50
78
Preliminary
14
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
