DM9010
Single Chip Ethernet Controller with General Processor Interface
1: Reverse MII mode
0: normal MII mode
53
TXD[3]
External MII mode (not available in 32-bit mode)
force to external MII mode , mapping to bit 5 of REG. 2EH
and set register NCR Bit7 “1”,
54
74
TXEN
Disable to load EEPROM after power on reset.
GPIO4
PHY Power-Up.
1: PHY is power-up after power-ON
0: PHY is power-down after power-ON
Output Type of INT
1: INT pin is Open-Collect
0: INT pin is force output
HP Auto-MDIX
75
77
GPIO5
GPIO6
0: HP Auto-MDIX turn ON
1: HP Auto-MDIX turn OFF
6. Vendor Control and Status Register Set
The DM9010 implements several control and status
registers, which can be accessed by the host. These CSRs
are byte aligned. All CSRs are set to their default values by
hardware or software reset unless they are specified
Register
Description
Offset
Default value
after reset
00H
00H
00H
00H
00H
00H
00H
00H
37H
38H
00H
00H
40H
XXH
XXH
NCR
NSR
TCR
TSR I
TSR II
RCR
Network Control Register
Network Status Register
TX Control Register
TX Status Register I
TX Status Register II
RX Control Register
RX Status Register
Receive Overflow Counter Register
Back Pressure Threshold Register
Flow Control Threshold Register
RX Flow Control Register
EEPROM & PHY Control Register
EEPROM & PHY Address Register
EEPROM & PHY Low Byte Data Register
EEPROM & PHY High Byte Data Register
Wake Up Control Register
Physical Address Register
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H-15H
RSR
ROCR
BPTR
FCTR
FCR
EPCR
EPAR
EPDRL
EPDRH
WCR
PAR
00H
Determined by
EEPROM
XXH
01H
XXH
MAR
GPCR
GPR
Multicast Address Register
General Purpose Control Register
General Purpose Register
16H-1DH
1EH
1FH
TRPAL
TRPAH
RWPAL
RWPAH
TX SRAM Read Pointer Address Low Byte
TX SRAM Read Pointer Address High Byte
RX SRAM Write Pointer Address Low Byte
RX SRAM Write Pointer Address High Byte
22H
23H
24H
25H
00H
00H
00H
0CH
Preliminary
15
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
