DM9010
Single Chip Ethernet Controller with General Processor Interface
4
3
2
1
0
DIS_CRC
ALL
RUNT
PRMSC
RXEN
PHS0,RW Discard CRC Error Packet
PHS0,RW Pass All Multicast
PHS0,RW Pass Runt Packet
PHS0,RW Promiscuous Mode
PHS0,RW RX Enable
6.7 RX Status Register ( 06H )
Bit
Name
Default
Description
7
RF
PHS0,RO Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
PHS0,RO Multicast Frame
It is set to indicate that the received frame has a multicast address
PHS0,RO Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
PHS0,RO Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
PHS0,RO Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
PHS0,RO Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
PHS0,RO CRC Error
It is set to indicate that the received frame ends with a CRC error
PHS0,RO FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6
5
4
3
2
1
0
MF
LCS
RWTO
PLE
AE
CE
FOE
6.8 Receive Overflow Counter Register ( 07H )
Bit
7
Name
RXFU
Default
PHS0,R/C Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
PHS0,R/C Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
Description
6:0
ROC
6.9 Back Pressure Threshold Register (08H)
Bit
7:4
Name
BPHW
Default
PHS3,
RW
Description
Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
Preliminary
19
Version: DM9010-17--DS-P04
Jan. 18, 2006
DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
