DM9010
Single Chip Ethernet Controller with General Processor Interface
1
1
reserved
66
67
EECK
EECS
O,PD Clock to EEPROM
O,PD Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface
21
22
59
X2_25M
X1_25M
O
I
Crystal 25MHz Out
Crystal 25MHz In
CLK20MO
I/O,PD 20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
When pin TEST5 state is high, this pin act as the system clock.
5.5 LED Interface
60
SPLED
O
O
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
Link / Active LED
61
FDLED
LKLED
62
O
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
5.6 10/100 PHY/Fiber
24
SD
I
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Bandgap Ground
25
26
BGGND
BGRES
RXVDD25
RXI+
P
I/O Bandgap Pin
27,28
29
P
Internal regulator 2.5V output for TP RX
I/O TP RX Input
I/O TP RX Input
30
RXI-
31
RXGND
TXGND
TXO+
P
P
RX Ground
TX Ground
32
33
I/O TP TX Output
I/O TP TX Output
34
TXO-
Preliminary
13
Version: DM9010-17--DS-P04
Jan. 18, 2006