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DM9010 参数 Datasheet PDF下载

DM9010图片预览
型号: DM9010
PDF下载: 下载PDF文件 查看货源
内容描述: 10/100 Mbps的单芯片以太网控制器与通用处理器接口 [10/100 Mbps Single Chip Ethernet Controller with General Processor Interface]
分类和应用: 控制器以太网局域网(LAN)标准
文件页数/大小: 62 页 / 511 K
品牌: DAVICOM [ DAVICOM SEMICONDUCTOR, INC. ]
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DM9010  
Single Chip Ethernet Controller with General Processor Interface  
5. Pin Description  
I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power,  
LI= reset Latch Input, #= asserted low, PD=internal pull-low about 60K ohm, PU=internal pull-high  
5.1 MII Interface  
Pin No.  
Pin Name  
I/O  
Description  
37  
LINK_I  
I,PD External MII device link status  
I,PD External MII Receive Data  
41,40,39,  
RXD [3:0]  
38  
43  
4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode  
I/O,PD External MII Carrier Sense  
CRS  
Active high to indicate the pressure of carrier, due to receive or transmit activities  
in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface.  
I/O,PD External MII Collision Detect. This pin is output in reverse MII interface.  
44  
45  
46  
47  
49  
COL  
RX_DV  
RX_ER  
RX_CLK  
TX_CLK  
TXD [3:0]  
I,PD External MII Receive Data Valid  
I,PD External MII Receive Error  
I,PD External MII Receive Clock  
I/O,PD External MII Transmit Clock. This pin in output in MII interface.  
53,52,51,  
50  
O,PD External MII Transmit Data  
4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps  
nibble mode  
TXD [2:0] is also used as the strap pins of IO base address.  
IO base = (strap pin value of TXD [2:0]) * 10H + 300H  
O,PD External MII Transmit Enable  
54  
56  
57  
TX_ EN  
MDIO  
MDC  
I/O,PD MII Serial Management Data  
O,PD MII Serial Management Data Clock  
This pin is also used as the strap pin of the polarity of the INT pin  
When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin  
is high active  
5.2 Processor Interface  
1
2
3
4
IOR#  
IOW#  
AEN  
I,PD Processor Read Command  
This pin is low active at default; its polarity can be modified by EEPROM setting.  
See the EEPROM content description for detail  
I,PD Processor Write Command  
This pin is low active at default; its polarity can be modified by EEPROM setting.  
See the EEPROM content description for detail  
I,PD Address Enable  
A low active signal used to select the DM9010.  
IOWAIT  
O,PD Processor Command Ready  
When a command is issued before last command is completed, the IOWAIT will  
be pulled low to indicate the current command is waited  
The polarity and output type can be updated by EEPROM. The default is  
Preliminary  
11  
Version: DM9010-17--DS-P04  
Jan. 18, 2006