U631H16
Nonvolatile Memory Operations
Symbol
STORE Cycle Inhibit and
No.
Min.
Max.
Unit
Automatic Power Up RECALL
Alt.
tRESTORE
VSWITCH
IEC
24 Power Up RECALL Durationk, e
650
4.5
µs
Low Voltage Trigger Level
4.0
V
k: tRESTORE starts from the time VCC rises above VSWITCH
.
STORE Cycle Inhibit and Automatic Power Up RECALL
VCC
5.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Software Mode Selection
A10 - A0
(hex)
E
W
Mode
I/O
Power
Notes
L
H
000
555
2AA
7FF
0F0
70F
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
ICC2
L
H
000
555
2AA
7FF
0F0
70E
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
l, m
l, m
l, m
l, m
l, m
l
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
l: The six consecutive addresses must be in order listed (000, 555, 2AA, 7FF, 0F0, 70F) for a Store cycle or (000, 555, 2AA,
7FF, 0F0, 70E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and
diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 000, 555, 2AA, 7FF, 0F0, 39C.
m: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
7
April 20, 2004
CYPRESS [ CYPRESS ]
