U631H16
Write Cycle #1: W-controlledj
tcW
(12)
Address Valid
tsu(E)
Ai
E
t
(17)
h(A) (21)
tsu(A-WH)
(16)
tw(W)
(13)
W
t
su(A) (15)
tsu(D)
th(D)
(19)
Input Data Valid
ten(W)
(20)
DQi
Input
tdis(W)
(22)
(23)
High Impedance
DQi
Previous Data Valid
Output
Write Cycle #2: E-controlledj
tcW
(12)
Ai
E
Address Valid
t
su(A) (15)
tw(E)
th(A)
(18)
(21)
tsu(W)
(14)
W
t
t
h(D) (20)
su(D)(19)
DQi
Input
Input Data Valid
High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
>
VIH during address transitions.
j: E or W must be
6
April 20, 2004