CY7C9689
TXCLK
TXRST
CE
[46]
Tx_Match
Note 47
TXEN
[46]
Tx_Selected
TXDATA/TXCMD
(Shared Bus Timing)
D1
D2
D1
D3
D2
TXDATA/TXCMD
(Cascade Timing)
D3
TXFULL
Not Full
Not Full
Note 47
Figure 8. Transmit Selection with Transmit FIFO Enabled
REFCLK
TXRST
CE
Tx_Match
TXEN
[46]
[46]
Note 47
Tx_Selected
TXDATA/TXCMD
(Shared Bus Timing)
D1
D2
D1
D3
D2
TXDATA/TXCMD
(Cascade Timing)
D3
Not Full
Note 47
Not Full
TXFULL
Figure 9. Transmit Selection with Transmit FIFO Bypassed
Notes:
46.Signals labeled in italics are internal to the CY7C9689.
47.Signals shown as dotted lines represent the differences in timing and active state of signals when operated in Cascade Timing.
41
CYPRESS [ CYPRESS ]
