CY7C9689
T X C LK
T X R ST
Note 48
T X EN
C E
[49]
[49]
T x_R stM atch
T x_ M atch
[49]
Tx_ FIFO _ R eset
T X F U L L
Note 48
N ot Full
Full
Figure 14. Transmit FIFO Reset Sequence with Constant CE
a reset operation. This is shown by the TXFULL flag remaining
HIGH (deasserted) following what would be the normal expi-
ration of the seven-state reset counter.
T X C L K
T X R S T
TX E N
C E
Note 48
[49]
Tx_ RstM a tch
Tx_M a tch
[49]
[49]
T x_ F IF O _R eset
TX F U LL
Note 48
N ot Full
F ull
Figure 13. Transmit FIFO Reset Sequence
Notes:
48. Signals shown as dotted lines indicate timing and levels when configured for external FIFOs (EXTFIFO is HIGH).
49. Signal names listed in italics are internal signals, shown for reference only.
44
CYPRESS [ CYPRESS ]
