CY7C9689
more clock cycles prior to the selection control signal being
sampled asserted.
TXCLK
CE
Transmit Data Selection
Asynchronous With Shared Bus Timing and Control
(Transmit FIFO Enabled)
TXFULL
Va lid
When CE is sampled LOW and TXRST is sampled HIGH by
the rising edge of TXCLK, a Tx_Match condition is generated.
This Tx_Match condition continues until CE is sampled HIGH
or TXRST is sampled LOW at the rising edge of TXCLK. When
a Tx_Match (or Tx_RstMatch) condition is present, the
TXEMPTY and TXFULL output drivers are enabled. When a
Tx_Match (or Tx_RstMatch) condition is not present, these
same drivers are disabled (High-Z).
Transmit Port Addressing
RXCLK
CE
The selection state of the Transmit FIFO is entered when a
Tx_Match condition is present, and TXEN transitions from
HIGH to LOW. Once selected, the Transmit FIFO remains se-
lected until TXEN is sampled HIGH by the rising edge of
TXCLK. In the selected state, data present on the TXDATA
inputs is captured and stored in the Transmit FIFO. This trans-
mit interface selection process is shown in Figure 8.
Valid
RXEMPTY
Receive Port Addressing
Figure 7. FIFO Flag Driver Enables
Synchronous With Shared Bus Timing and Control
(Transmit FIFO Bypassed)
When the Transmit FIFO is bypassed (FIFOBYP is LOW and
not in byte-packed mode) and CE is sampled LOW by the ris-
ing edge of REFCLK, the output drivers for the TXFULL and
TXEMPTY FIFO flags are enabled. When CE is sampled
HIGH by the rising edge of REFCLK, the FIFO flag output driv-
ers are disabled.
When the Transmit FIFO is bypassed (FIFOBYP is LOW and
not in byte-packed mode), the CY7C9689 must still be select-
ed to write data into the Transmit Input Register.
When CE is sampled LOW and TXRST is sampled HIGH by
the rising edge of REFCLK, a Tx_Match condition is generat-
ed. This Tx_Match condition continues until CE is sampled
HIGH or TXRST is sampled LOW at the rising edge of TXCLK.
When a Tx_Match (or Tx_RstMatch) condition is present, the
TXEMPTY and TXFULL output drivers are enabled (with the
Transmit FIFO bypassed, the status flags normally indicate an
Empty condition). When a Tx_Match (or Tx_RstMatch) condi-
tion is not present, these same drivers are disabled (High-Z).
When CE is sampled LOW by the rising edge of RXCLK (input
or output), the output drivers for the RXFULL and RXEMPTY
FIFO flags are enabled. When CE is sampled HIGH by the
rising edge of RXCLK, the FIFO flag output drivers are dis-
abled.
Device Selection
The concept of selection is used to control the access to the
transmit and receive parallel-data ports of the device. There
are three primary types of selection:
The selection state of the Transmit Input Register is entered
when a Tx_Match condition is present, and TXEN transitions
from HIGH to LOW. Once selected, the transmit input register
remains selected until TXEN is sampled HIGH by the rising
edge of REFCLK. In the selected state, data present on the
TXDATA inputs is captured in the Transmit Input Register and
passed to the Serializer or Encoder (as selected by the
ENCBYP input). This transmit interface selection process is
shown in Figure 9.
•Transmit data selection (with and without internal Transmit
FIFO)
•Receive data selection (with and without internal Receive
FIFO)
•Continuous selection (for either or both transmit and receive
interfaces)
When the 4B/5B Encoder is enabled and data is not written to
the Transmit Input Register, the data stream is automatically
padded with JK or LM SYNC characters. When the 4B/5B,
5B/6B Encoder is disabled and no data is written to the Trans-
mit Input Register, JK or LM SYNC characters are also auto-
matically padded with SYNC characters.
In addition to these normal selection types, there are two ad-
ditional sequences that are used to control the internal Trans-
mit and Receive FIFOs reset operations, and to control
read/write access to the Serial Address Register:
•Transmit reset sequence
•Receive reset sequence
Receive Data Selection
Of these operations, the transmit data selection and transmit
reset sequence are mutually exclusive and cannot exist at the
same time. The receive data selection and receive reset se-
quence are also mutually exclusive and cannot exist at the
same time. Either transmit operation can exist at the same time
as either receive operation.
Asynchronous With Shared Bus Timing and Control
(Receive FIFO Enabled)
When CE is sampled LOW and RXRST is sampled HIGH by
the rising edge of RXCLK input, an Rx_Match condition is gen-
erated. This Rx_Match condition continues until CE is sampled
HIGH or RXRST is sampled LOW at the rising edge of RXCLK
input. When an Rx_Match (or Rx_RstMatch) condition is
present, the RXEMPTY and RXFULL output drivers are en-
All normal forms of selection require that an Chip Enable must
be asserted (CE sampled LOW) either at the same time as the
selection control signal being sampled asserted, or one or
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CYPRESS [ CYPRESS ]
