CY7C9689
T X C LK
T X R ST
T X EN
C E
Note 48
[49]
T x_R stM atch
T x_ M atch
[49]
[49]
T x_ FIFO _ R eset
T X FU L L
Note 48
N ot F ull
Figure 15. Invalid Transmit FIFO Reset Sequence with TXEN Asserted
Receive FIFO Reset Sequence
EMPTY state to prohibit additional reads from the FIFO. Unlike
the Transmit FIFO, where the internal completion of the reset
operation is shown by first going FULL and later going EMPTY
when the internal reset is complete, there is no secondary in-
dication of the completion of the internal reset of the Receive
FIFO. The Receive FIFO is usable as soon as new data is
placed into it by the Receive Control State Machine.
The Receive FIFO reset sequence operates (for the most part)
the same as the Transmit FIFO reset sequence. The same
requirements exist for the assertion state of RXRST and se-
lection of the interface. A sample Receive FIFO reset se-
quence is shown in Figure 16. Upon recognition of a Receive
FIFO reset, the Receive FIFO flags are forced to indicate an
45
CYPRESS [ CYPRESS ]
