CY7C9689
the recognition occurs in the middle of a data field, the follow-
ing data is not transmitted at that time, but remains in the
Transmit FIFO. Once the TXBISTEN signal is removed, the
data in the Transmit FIFO is again available for transmission.
To ensure proper data handling at the destination, the transmit
host controller should either use TXHALT to prevent transmis-
sion of data at specific boundaries, or allow the Transmit FIFO
to completely empty before enabling BIST.
BIST Operation and Reporting
The CY7C9689DX HOTLink Transceiver incorporates the
same Built-In Self-Test (BIST) capability. This link diagnostic
uses a Linear Feedback Shift Register (LFSR) to generate a
511-character repeating sequence that is compared, charac-
ter-for-character, at the receiver.
BIST mode is intended to check the entire high-speed serial
link at full link-speed, without the use of specialized and expen-
sive test equipment. The complete sequence of characters
used in BIST are documented in Table 4.
With transmit BIST enabled, the Transmit FIFO remains avail-
able for loading of data. It may be written up to its normal max-
imum limit while the BIST operation takes place. To allow re-
moval of stale data from the Transmit FIFO, it may also be reset
during a BIST operation. The reset operation proceeds as doc-
umented, with the exception of the information presented on
the TXEMPTY FIFO status flag. Since this flag is used to
present BIST loop status, it continues to reflect the state of the
transmit BIST loop status until TXBISTEN is no longer recog-
nized internally. The completion of the reset operation may still
be monitored through the TXFULL FIFO status flag.
BIST Enable Inputs
There are separate BIST enable inputs for the transmit and
receive paths of the CY7C9689. These inputs are both active
LOW; i.e., BIST is enabled in its respective section of the de-
vice when the BIST enable input is determined to be at a logic-
0 level. Both BIST enable inputs are asynchronous; i.e., they
are synchronized inside the CY7C9689 to the internal state
machines.
The TXEMPTY flag, when used for transmit BIST progress
indication, continues to reflect the active HIGH or active LOW
settings determined by the UTOPIA or Cascade timing model
selected by EXTFIFO; i.e., when configured for the Cascade
timing model, the TXEMPTY and TXFULL FIFO flags are ac-
tive HIGH, when configured for the UTOPIA timing model the
TXEMPTY and TXFULL FIFO flags are active LOW. The illus-
tration in Figure 5 uses the UTOPIA conventions.
BIST Transmit Path
The transmit path operation with BIST is controlled by the
TXBISTEN input and overrides most other inputs (see Figure
5). When the Transmit FIFO is enabled (not bypassed) and
TXBISTEN is recognized internally, all reads from the Transmit
FIFO are suspended and the BIST generator is enabled to
sequence out the 511 character repeating BIST sequence. If
TXCLK
TXBISTEN
Enable TX BIST
BIST
LOOP
TXEMPTY
TXHALF
TXFULL
Start of TX BIST
OUTA±
OUTB±
TXCMD[1:0]
Don’t Care
TXSC/D
TXDATA[9:0]
TXEN
REFCLK
LOW to enable FIFO Flags CE
LOW to enable VLTN reads
RXEN
RXDATA[9:0]
RXSC/D
RXCMD[1:0]
VLTN
Ignore these outputs
ERROR
INA±
INB±
RXEMPTY
RXHALF
RXFULL
Forced to indicate EMPTY by BIST
Start of RX
BIST match
Start of RX
BIST Wait
BIST
LOOP
Enable RX BIST
RXBISTEN
RXCLK
HIGH to select A
A/B
Figure 5. Built-In Self-Test Illustration
37
CYPRESS [ CYPRESS ]
