CY7C9689
abled. When an Rx_Match (or Rx_RstMatch) condition is not
present, these same drivers are disabled (High-Z).
ister remains selected until RXEN is sampled HIGH by the
rising edge of RXCLK output. In the selected state, the output
drivers for the RXDATA outputs are enabled, and new data is
presented to the RXDATA bus on every clock cycle.
The selection state of the Receive FIFO is entered when an
Rx_Match condition is present, and RXEN transitions from
HIGH to LOW. Once selected, the Receive FIFO remains se-
lected until RXEN is sampled HIGH by the rising edge of
RXCLK input. The selected state initiates a read cycle from the
Receive FIFO and enables the Receive FIFO data onto the
RXDATA bus. This receive interface selection process is
shown in Figure 10.
Continuous Selection
Continuous Selection is a specialized form of selection which
does not require sequenced assertion of CE and TXEN or
RXEN to select the device for data transfers. In this Continuous
Selection mode, the CE and associated TXEN or RXEN en-
able signal must be asserted when the device is powered up
or during assertion of RESET. So long as these signals remain
asserted, the device remains selected and data is accepted
and presented on every clock cycle.
Synchronous With UTOPIA Timing and Control
(Receive FIFO Bypassed)
When the Receive FIFO is bypassed (FIFOBYP is LOW), the
CY7C9689 must still be selected to enable the output drivers
for the RXDATA bus. With the Receive FIFO bypassed, RXCLK
becomes a synchronous output clock operating at the charac-
ter rate.
NOTE:
The use of continuous selection makes it impossible to
reset the respective internal FIFOs, or to access the Serial
Address Register.
FIFO Reset Address Match
When CE is sampled LOW and RXRST is sampled HIGH by
the rising edge of RXCLK output, an Rx_Match condition is
generated. This Rx_Match condition continues until CE is
sampled HIGH or RXRST is sampled LOW at the rising edge
of RXCLK.
When CE and TXRST are both LOW, and this condition is
sampled by the rising edge of TXCLK, a Tx_RstMatch condi-
tion is generated. This Tx_RstMatch condition continues until
CE or TXRST is sampled HIGH by the rising edge of TXCLK.
When a Tx_RstMatch (or Tx_Match) condition is present, the
TXEMPTY and TXFULL output drivers are enabled (just as in
a normal Tx_Match condition). When a Tx_RstMatch (or
Tx_Match) condition is not present, these same drivers are
disabled (High-Z). The Transmit FIFO reset Address Match is
shown in Figure 11. Note that although TXRST remains LOW
for more than one clock cycle, the Tx_RstMatch does not be-
cause the CE signal is no longer asserted (LOW).
When an Rx_Match (or Rx_RstMatch) condition is present,
the RXEMPTY and RXFULL output drivers are enabled. With
the Receive FIFO bypassed, these flags normally indicate a
non-empty condition but may indicate empty if a JK or LM
SYNC character is present in the output register and the re-
ceiver discard policy is non-0. When an Rx_Match (or
Rx_RstMatch) condition is not present, these same drivers are
disabled (High-Z).
When CE and RXRST are both LOW, and this condition is
sampled by the rising edge of RXCLK, an Rx_RstMatch con-
dition is generated. This Rx_RstMatch condition continues un-
til CE or RXRST is sampled HIGH, at the rising edge of RX-
The selection state of the Receive Output Register is entered
when an Rx_Match condition is present, and RXEN transitions
from HIGH to LOW. Once selected, the Receive Output Reg-
RXCLK
RXRST
CE
[46]
Rx_Match
RXEN
Rx_Selected
Note 47
[46]
RXDATA/RXCMD
RXEMPTY
D1
D2
D3
Not Empty
Note 47
Not Empty
Figure 10. Receive Selection with Receive FIFO Enabled
42
CYPRESS [ CYPRESS ]
