CY7C9689
Policy 2 is identical to policy 1 except that all C5.0 characters
are removed from the data stream.
CY7C42x5 FIFO
EF* FF*
REN* WEN*
CY7C9689
When the FIFOs are bypassed (FIFOBYP LOW), no charac-
ters are actually discarded, but the receiver discard policy can
be used to control external filtering of the data. The RXEMPTY
FIFO flag is used to indicate if the character on the output bus
is valid or not. In discard policy 0, the RXEMPTY flag is always
deasserted to indicate that valid data is always present. In dis-
card policy 1, the RXEMPTY flag indicates an empty condition
for all but the last JK or LM character before any other charac-
ter is presented. In discard policy 2, the RXEMPTY flag indi-
cates an empty condition for all JK or LM SYNC characters.
When any other character is present, this flag indicates that
valid or “interesting” Data or Special Characters are present.
EF*
RXEN
REN*
RXEMPTY
D
D
Q
RXDATA
RXSC/D
RXCLK
RCLK WCLK
RXCLK
“1”
EXTFIFO
Receive FIFO
The Receive FIFO is used to buffer data captured from the
selected serial stream for later processing by the host system.
This FIFO is sized to hold 256 14-bit characters. When the
FIFO is enabled, it is written to by the Receive Control State
Machine. When data is present in the Receive FIFO (as indi-
cated by the RXFULL, RXHALF, and RXEMPTY Receive FIFO
status flags), it can be read from the Output Register by as-
serting CE and RXEN.
Figure 4. External FIFO Depth Expansion of the CY7C9689
Receive Data Path
Receive Output Register
The Receive Output Register changes in response to the ris-
ing edge of RXCLK. The Receive FIFO status flag outputs of
this register are placed in a High-Z state when the CY7C9689
is not addressed (CE is sampled HIGH). The RXDATA bus
output drivers are enabled when the device is selected by
RXEN being asserted in the RXCLK cycle immediately follow-
ing that in which the device was addressed (CE is sampled
LOW), and RXEN being sampled by RXCLK. This initiates a
Receive FIFO read cycle.
The read port on the Receive FIFO may be configured for the
same two timing models as the transmit interface: UTOPIA and
Cascade. Both are forms of a FIFO interface. The UTOPIA
timing model has active LOW RXEMPTY and RXFULL status
flags, and an active LOW RXEN enable. When configured for
Cascade operation, these same signals are all active HIGH.
Either timing model supports connection to various host bus
interfaces, state machines, or external FIFOs for depth expan-
sion (see Figure 4).
Just as with the TXDATA bus on the Transmit Input Register,
the receive outputs are also mapped by the specific decoding,
parity, and bus-width selected by the ENCBYP, BYTE8/10 and
FIFOBYP inputs. These assignments are shown in Table 6.
The Receive FIFO presents Full, Half-Full, and Empty FIFO
status flags. These flags are provided synchronous to RXCLK
to allow operation with a Moore-type external controlling state
machine. When configured with the Receive FIFO enabled,
RXCLK is an input. When the Receive FIFO is bypassed
(FIFOBYP is LOW), RXCLK is an output operating at the re-
ceived character rate.
If the Receive FIFO and Decoder are bypassed, all received
characters are passed directly to the Receive Output Register.
If framing is enabled, and JK or LM sync characters have been
detected meeting the present framing requirements, the out-
put characters will appear on proper character boundaries. If
framing is disabled (RFEN is LOW) or sync characters have
not been detected in the data stream, the received characters
may not be output on their proper 10-bit boundaries. In this
mode, some form of external framing and decoding/descram-
bling must be used to recover the original source data.
Receive Input Register
The input register is clocked by the rising edge of RXCLK. It
samples numerous signals that control the reading of the Re-
ceive FIFO and operation of the Receive Control State Ma-
chine.
20
CYPRESS [ CYPRESS ]
