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CY7C9689-AC 参数 Datasheet PDF下载

CY7C9689-AC图片预览
型号: CY7C9689-AC
PDF下载: 下载PDF文件 查看货源
内容描述: TAXI兼容的HOTLink收发器 [TAXI Compatible HOTLink Transceiver]
分类和应用:
文件页数/大小: 48 页 / 962 K
品牌: CYPRESS [ CYPRESS ]
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CY7C9689  
CY7C9689 Receiver TTL Switching Characteristics, FIFO Enabled Over the Operating Range  
Parameter  
Description  
RXCLK Clock Cycle Frequency With Receive FIFO Enabled  
RXCLK Input Period  
Min.  
Max.  
Unit  
MHz  
ns  
f
t
t
t
t
t
t
t
t
t
t
t
t
t
50  
RIS  
20  
6.5  
6.5  
0.7  
0.7  
4
RXCLKIP  
RXCPWH  
RXCPWL  
RXCLK Input HIGH Time  
ns  
RXCLK Input LOW Time  
ns  
[16]  
RXCLKIR  
[18]  
RXCLK Input Rise Time  
5
5
ns  
[16]  
[18]  
RXCLK Input Fall Time  
ns  
RXCLKIF  
RXENS  
RXENH  
RXRSS  
RXRSH  
RXCES  
RXCEH  
RXA  
Receive Enable Set-Up Time to RXCLK↑  
ns  
Receive Enable Hold Time from RXCLK↑  
1
ns  
Receive FIFO Reset (RXRXT) Set-Up Time to RXCLK↑  
Receive FIFO Reset (RXRXT) Hold Time from RXCLK↑  
Receive Chip Enable (CE) Set-Up Time to RXCLK↑  
Receive Chip Enable (CE) Hold Time from RXCLK↑  
Flag and Data Access Time From RXCLKto Output  
Sample of CE LOW by RXCLK, Output High-Z to Active HIGH or LOW,  
4
ns  
1
ns  
4
ns  
1
ns  
1.5  
0
15  
ns  
[19]  
ns  
RXZA  
or Sample of RXEN Asserted by RXCLK, Output High-Z to Active HIGH  
or LOW  
[19]  
t
t
Sample of CE LOW by RXCLKto Output Valid,  
1.5  
1.5  
20  
20  
ns  
ns  
RXOE  
or Sample of RXEN Asserted by RXCLKto RXDATA Outputs Valid  
[19]  
Sample of CE HIGH by RXCLKto Output in High-Z,  
RXZA  
or Sample of RXEN Asserted by RXCLKto RXDATA Outputs in High-Z  
CY7C9689 Transmitter TTL Switching Characteristics, FIFO Bypassed Over the Operating Range  
Parameter  
Description  
Min.  
2
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
Flag Access Time From REFCLKto Output  
Write Data Set-Up Time to REFCLK↑  
15  
TRA  
4
REFDS  
Write Data Hold Time from REFCLK↑  
2
REFDH  
Transmit Enable Set-Up Time to REFCLK↑  
4
REFENS  
REFENH  
REFCES  
REFCEH  
REFZA  
Transmit Enable Hold Time from REFCLK↑  
2
Transmit Chip Enable (CE) Set-Up Time to REFCLK↑  
Transmit Chip Enable (CE) Hold Time from REFCLK↑  
Sample of CE LOW by REFCLK, Output High-Z to Active HIGH or LOW  
Sample of CE LOW by REFCLKto Flag Output Valid  
Sample of CE HIGH by REFCLKto Flag Output High-Z  
4
2
0
1.5  
1.5  
20  
20  
REFOE  
REFAZ  
Note:  
19. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.  
24  
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