CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.16
Sequence Diagram
9.16.1 Single and Burst Synchronous Read Example
t
IFCLK
IFCLK
t
t
SFA
SFA
t
t
FAH
FAH
FIFOADR
t=0
T=0
t
t
>= t
SRD
>= t
RDH
RDH
SRD
SLRD
SLCS
t=3
t=2
T=3
T=2
t
XFLG
FLAGS
DATA
SLOE
t
t
t
t
XFD
XFD
XFD
XFD
N+4
Data Driven: N
OEon
N+1
N+1
N+2
N+3
t
t
OEon
t
OEoff
t
OEoff
t=4
T=4
T=1
t=1
Figure 9-16. Slave FIFO Synchronous Read Sequence and Timing Diagram
IFCLK
N
IFCLK
N
IFCLK
N+1
IFCLK
N+1
IFCLK
N+1
IFCLK
N+2
IFCLK
N+3
IFCLK
N+4
IFCLK
N+4
IFCLK
N+4
FIFO POINTER
SLOE
SLRD
SLOE
SLRD
SLOE
SLRD
SLRD
N+4
SLOE
FIFO DATA BUS Not Driven
Driven: N
N+1
Not Driven
N+1
N+2
N+3
N+4
Not Driven
Figure 9-17. Slave FIFO Synchronous Sequence of Events Diagram
Figure 9-16 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
with SLRD, or before SLRD is asserted (i.e., the SLCS and
SLRD signals must both be asserted to start a valid read
condition).
• The FIFO pointeris updated ontherising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
• At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note: t
hasaminimum of25ns. Thismeanswhen IFCLK
propagation delay of t
(measured from the rising edge
SFA
XFD
is running at 48 MHz, the FIFO address set-up time is more
than one IFCLK cycle.
of IFCLK) the new data value is present. N is the first data
value read from the FIFO. In order to have data on the FIFO
data bus, SLOE MUST also be asserted.
• At = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that
is driven on the bus is the data that the internal FIFO pointer
is currently pointing to. In this example it is the first data
value in the FIFO. Note: the data is pre-fetched and is driven
on the bus when SLOE is asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5. Note:
For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is
on the data bus. During the first read cycle, on the rising edge
of the clock the FIFO pointer is updated and increments to
point to address N+1. For each subsequent rising edge of
IFCLK, while the SLRD is asserted, the FIFO pointer is incre-
mented and the next data value is placed on the data bus.
• At t = 2, SLRD is asserted. SLRD must meet the set-up time
of t
(time from asserting the SLRD signal to the rising
SRD
edge of the IFCLK) and maintain a minimum hold time of
(time from the IFCLK edge to the deassertion of the
t
RDH
SLRDsignal). If theSLCS signalis used, itmustbe asserted
Document #: 38-08032 Rev. *G
Page 47 of 55
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