CY7C68013A/CY7C68014A
CY7C68015A/CY7C68016A
9.14
Slave FIFO Synchronous Address
IFCLK
SLCS/FIFOADR [1:0]
tSFA
tFAH
Figure 9-14. Slave FIFO Synchronous Address Timing Diagram
[21]
Table 9-17. Slave FIFO Synchronous Address Parameters
Parameter Description
Interface Clock Period
Min.
20.83
25
Max.
Unit
ns
t
t
t
200
IFCLK
FIFOADR[1:0] to Clock Set-up Time
Clock to FIFOADR[1:0] Hold Time
ns
SFA
FAH
10
ns
9.15
Slave FIFO Asynchronous Address
SLCS/FIFOADR [1:0]
tFAH
tSFA
SLRD/SLWR/PKTEND
[19]
Figure 9-15. Slave FIFO Asynchronous Address Timing Diagram
[23]
Slave FIFO Asynchronous Address Parameters
Parameter
Description
Min.
10
Max.
Unit
ns
t
t
FIFOADR[1:0] to SLRD/SLWR/PKTEND Set-up Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
SFA
FAH
10
ns
Document #: 38-08032 Rev. *G
Page 46 of 55
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