CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.10 Slave FIFO Asynchronous Write
Figure 9-10. Slave FIFO Asynchronous Write Timing Diagram[20]
t
WRpwh
SLWR
SLWR/SLCS#
t
WRpwl
t
t
FDH
SFD
DATA
t
XFD
FLAGS
Table 24. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [23]
Parameter
tWRpwl
tWRpwh
tSFD
Description
Min
50
70
10
10
–
Max
–
Unit
ns
SLWR pulse LOW
SLWR pulse HIGH
–
ns
SLWR to FIFO DATA setup time
FIFO DATA to SLWR hold time
–
ns
tFDH
–
ns
tXFD
SLWR to FLAGS output propagation delay
70
ns
9.11 Slave FIFO Synchronous Packet End Strobe
Figure 9-11. Slave FIFO Synchronous Packet End Strobe Timing Diagram[20]
IFCLK
t
PEH
PKTEND
FLAGS
t
SPE
t
XFLG
Table 25. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min
20.83
14.6
0
Max
–
Unit
ns
IFCLK period
tSPE
tPEH
tXFLG
PKTEND to clock setup time
–
ns
Clock to PKTEND hold time
–
ns
Clock to FLAGS output propagation delay
–
9.5
ns
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min
20.83
8.6
Max
200
–
Unit
ns
IFCLK period
tSPE
tPEH
tXFLG
PKTEND to clock setup time
ns
Clock to PKTEND hold time
2.5
–
ns
Clock to FLAGS output propagation delay
–
13.5
ns
Document #: 38-08032 Rev. *V
Page 47 of 66
CYPRESS [ CYPRESS ]
