CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 9-18 on page 50 shows the timing relationship of the
SLAVE FIFO signals during a synchronous FIFO read using
IFCLK as the synchronizing clock. The diagram illustrates a
single read followed by a burst read.
■ The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge of
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
MUST also be asserted.
■ At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications). Note
that tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle, on the rising edge of the
clock the FIFO pointer is updated and increments to point to
address N+1. For each subsequent rising edge of IFCLK, while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
■ At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO. Note: the data is pre-fetched and is driven on the bus
when SLOE is asserted.
■ At t = 2, SLRD is asserted. SLRD must meet the setup time of
tSRD (time from asserting the SLRD signal to the rising edge of
the IFCLK) and maintain a minimum hold time of tRDH (time
from the IFCLK edge to the deassertion of the SLRD signal).
If the SLCS signal is used, it must be asserted before SLRD is
asserted (The SLCS and SLRD signals must both be asserted
to start a valid read condition).
9.17.2 Single and Burst Synchronous Write
Figure 9-20. Slave FIFO Synchronous Write Sequence and Timing Diagram[20]
t
IFCLK
IFCLK
t
t
SFA
t
SFA
t
FAH
FAH
FIFOADR
>= t
t=0
WRH
t
t
>= t
T=0
SWR
WRH
SWR
SLWR
SLCS
T=2
T=5
t=2
t=3
t
XFLG
t
XFLG
FLAGS
DATA
t
t
t
t
t
FDH
t
t
t
SFD
SFD
FDH
FDH
SFD
SFD
FDH
N+1
N+3
N
N+2
T=4
T=3
t=1
T=1
t
SPE
t
PEH
PKTEND
Document #: 38-08032 Rev. *V
Page 51 of 66
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