CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min
20.83
12.7
3.7
–
Max
200
–
Unit
ns
IFCLK period
tSRD
tRDH
tOEon
tOEoff
tXFLG
tXFD
SLRD to clock setup time
ns
Clock to SLRD hold time
–
ns
SLOE turn on to FIFO data valid
SLOE turn off to FIFO data hold
Clock to FLAGS output propagation delay
Clock to FIFO data output propagation delay
10.5
10.5
13.5
15
ns
–
ns
–
ns
–
ns
9.8 Slave FIFO Asynchronous Read
Figure 9-8. Slave FIFO Asynchronous Read Timing Diagram[20]
t
RDpwh
SLRD
t
RDpwl
t
XFLG
t
FLAGS
XFD
DATA
SLOE
N+1
N
t
t
OEoff
OEon
Table 21. Slave FIFO Asynchronous Read Parameters[23]
Parameter Description
tRDpwl SLRD pulse width LOW
SLRD pulse width HIGH
Min
Max
–
Unit
ns
50
50
–
tRDpwh
tXFLG
tXFD
–
ns
SLRD to FLAGS output propagation delay
SLRD to FIFO data output propagation delay
SLOE turn-on to FIFO data valid
70
ns
–
15
ns
tOEon
tOEoff
–
10.5
10.5
ns
SLOE turn-off to FIFO data hold
–
ns
Note
23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document #: 38-08032 Rev. *V
Page 45 of 66
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