CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.9 Slave FIFO Synchronous Write
Figure 9-9. Slave FIFO Synchronous Write Timing Diagram[20]
t
IFCLK
IFCLK
SLWR
t
WRH
t
SWR
DATA
N
Z
Z
t
t
FDH
SFD
FLAGS
t
XFLG
Table 22. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min
20.83
10.4
0
Max
–
Unit
ns
IFCLK period
tSWR
tWRH
tSFD
SLWR to clock setup time
–
ns
Clock to SLWR hold time
–
ns
FIFO data to clock setup time
Clock to FIFO data hold time
Clock to FLAGS output propagation time
9.2
0
–
ns
tFDH
tXFLG
–
ns
–
9.5
ns
Table 23. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[21]
Parameter
tIFCLK
Description
Min
20.83
12.1
3.6
Max
200
–
Unit
ns
IFCLK Period
tSWR
tWRH
tSFD
SLWR to clock setup time
ns
Clock to SLWR hold time
–
ns
FIFO data to clock setup time
Clock to FIFO data hold time
Clock to FLAGS output propagation time
3.2
–
ns
tFDH
tXFLG
4.5
–
ns
–
13.5
ns
Document #: 38-08032 Rev. *V
Page 46 of 66
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