CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.16 Slave FIFO Asynchronous Address
Figure 9-17. Slave FIFO Asynchronous Address Timing Diagram[20]
SLCS/FIFOADR [1:0]
t
FAH
t
SFA
SLRD/SLWR/PKTEND
Table 31. Slave FIFO Asynchronous Address Parameters[23]
Parameter
Description
Min
10
Max
–
Unit
ns
tSFA
tFAH
FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time
RD/WR/PKTEND to FIFOADR[1:0] hold time
10
–
ns
9.17 Sequence Diagram
9.17.1 Single and Burst Synchronous Read Example
Figure 9-18. Slave FIFO Synchronous Read Sequence and Timing Diagram[20]
t
IFCLK
IFCLK
t
t
SFA
SFA
t
t
FAH
FAH
FIFOADR
t=0
T=0
t
t
>= t
SRD
>= t
RDH
RDH
SRD
SLRD
SLCS
t=3
t=2
T=3
T=2
t
XFLG
FLAGS
DATA
SLOE
t
t
XFD
t
XFD
t
XFD
XFD
N+4
Data Driven: N
N+2
N+3
N+1
N+1
t
t
t
OEon
t
OEoff
OEoff
OEon
t=4
T=4
T=1
t=1
Figure 9-19. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK
IFCLK
N
IFCLK
N+1
IFCLK
N+1
IFCLK
N+1
IFCLK
N+2
IFCLK
N+3
IFCLK
N+4
IFCLK
N+4
IFCLK
N+4
N
FIFO POINTER
SLOE
SLRD
SLOE
SLRD
SLOE
SLRD
SLRD
SLOE
FIFO DATA BUS Not Driven
Driven: N
N+1
Not Driven
N+1
N+2
N+3
N+4
N+4
Not Driven
Document #: 38-08032 Rev. *V
Page 50 of 66
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