CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.1 Slave FIFO Synchronous Read
Figure 9-7. Slave FIFO Synchronous Read Timing Diagram
t
IFCLK
IFCLK
t
SRD
SLRD
t
XFLG
FLAGS
t
RDH
DATA
t
OEon
SLOE
N
N+1
t
XFD
t
OEoff
Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
t
IFCLK
t
SRD
t
RDH
t
OEon
t
OEoff
t
XFLG
t
XFD
t
IFCLKR
t
IFCLKF
t
IFCLKOD
t
IFCLKJ
IFCLK period
SLRD to clock setup time
Clock to SLRD hold time
SLOE turn on to FIFO data valid
SLOE turn off to FIFO data hold
Clock to FLAGS output propagation delay
Clock to FIFO data output propagation delay
IFCLK rise time
IFCLK fall time
IFCLK Output duty cycle
IFCLK jitter peak to peak
Description
Min
20.83
18.7
0
–
–
–
–
–
–
–
–
Max
–
–
–
10.5
10.5
9.5
11
–
–
–
–
Typ
Min
–
–
–
–
–
–
–
–
–
49
–
Max
–
–
–
–
–
–
–
900
900
51
300
Unit
ns
ns
ns
ns
ns
ns
ns
ps
ps
%
ps
Document #: 38-08032 Rev. *V
Page 44 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
