CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.13 Slave FIFO Output Enable
Figure 9-14. Slave FIFO Output Enable Timing Diagram
SLOE
t
OEoff
DATA
t
OEon
Table 28. Slave FIFO Output Enable Parameters
Parameter
t
OEon
t
OEoff
Description
SLOE assert to FIFO DATA output
SLOE deassert to FIFO DATA hold
Min
Max
10.5
10.5
Unit
ns
ns
9.14 Slave FIFO Address to Flags/Data
Figure 9-15. Slave FIFO Address to Flags/Data Timing Diagram
FIFOADR [1.0]
t
XFLG
FLAGS
t
XFD
DATA
N
N+1
Table 29. Slave FIFO Address to Flags/Data Parameters
Parameter
t
XFLG
t
XFD
Description
FIFOADR[1:0] to FLAGS output propagation delay
FIFOADR[1:0] to FIFODATA output propagation delay
Min
–
–
Max
10.7
14.3
Unit
ns
ns
9.15 Slave FIFO Synchronous Address
Figure 9-16. Slave FIFO Synchronous Address Timing Diagram
IFCLK
SLCS/FIFOADR [1:0]
t
SFA
t
FAH
Table 30. Slave FIFO Synchronous Address Parameters
Parameter
t
IFCLK
t
SFA
t
FAH
Interface clock period
FIFOADR[1:0] to clock setup time
Clock to FIFOADR[1:0] hold time
Description
Min
20.83
25
10
Max
200
–
–
Unit
ns
ns
ns
Document #: 38-08032 Rev. *V
Page 49 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
