CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.6 GPIF Synchronous Signals
Figure 9-6. GPIF Synchronous Signals Timing Diagram
t
IFCLK
IFCLK
t
SGA
GPIFADR[8:0]
RDY
X
t
SRY
t
RYH
DATA(input)
t
SGD
valid
t
DAH
CTL
X
t
XCTL
DATA(output)
N
t
XGD
N+1
Table 17. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
Parameter
t
IFCLK
t
SRY
t
RYH
t
SGD
t
DAH
t
SGA
t
XGD
t
XCTL
t
IFCLKR
t
IFCLKF
t
IFCLKOD
t
IFCLKJ
Description
IFCLK Period
RDY
X
to Clock Setup Time
Clock to RDY
X
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
X
Output Propagation Delay
IFCLK rise time
IFCLK fall time
IFCLK Output duty cycle
IFCLK jitter peak to peak
Min
20.83
8.9
0
9.2
0
–
–
–
–
–
–
–
Max
–
–
–
–
–
7.5
11
6.7
–
–
–
–
Typ
Min
–
–
–
–
–
–
–
–
–
–
49
–
Max
–
–
–
–
–
–
–
–
900
900
51
300
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
%
ps
Table 18. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Parameter
t
IFCLK
t
SRY
t
RYH
t
SGD
t
DAH
t
SGA
t
XGD
t
XCTL
Description
IFCLK Period
RDY
X
to Clock Setup Time
Clock to RDY
X
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
X
Output Propagation Delay
Min
20.83
2.9
3.7
3.2
4.5
–
–
–
Max
200
–
–
–
–
11.5
15
10.7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
20. Dashed lines denote signals with programmable polarity.
21. GPIF asynchronous RDY
x
signals have a minimum setup time of 50 ns when using internal 48 MHz IFCLK.
22. IFCLK must not exceed 48 MHz.
Document #: 38-08032 Rev. *V
Page 43 of 66
CYPRESS [ CYPRESS SEMICONDUCTOR ]
