欢迎访问ic37.com |
会员登录 免费注册
会员中心
企业资讯   人才招聘  
电子百科

电子百科

Datasheet下载 IC品牌 缩略语 技术文章 IC型号

产品导航

ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789
PDF
  • 产品
  • PDF

    • 最近搜索

    热门搜索

    搜索
    发布采购

    CY7C63723-PC 参数 Datasheet PDF下载

    CY7C63723-PC图片预览
    型号： CY7C63723-PC
    PDF下载： 下载PDF文件 查看货源
    内容描述： 的enCoRe USB的组合低速USB和PS / 2外围控制器 [enCoRe USB Combination Low-Speed USB & PS/2 Peripheral Controller]
    分类和应用： 微控制器和处理器外围集成电路光电二极管可编程只读存储器时钟
    文件页数/大小： 58 页 / 1162 K
    品牌： CYPRESS [ CYPRESS SEMICONDUCTOR ]
     浏览型号CY7C63723-PC的Datasheet PDF文件第1页浏览型号CY7C63723-PC的Datasheet PDF文件第2页浏览型号CY7C63723-PC的Datasheet PDF文件第3页浏览型号CY7C63723-PC的Datasheet PDF文件第5页浏览型号CY7C63723-PC的Datasheet PDF文件第6页浏览型号CY7C63723-PC的Datasheet PDF文件第7页浏览型号CY7C63723-PC的Datasheet PDF文件第8页浏览型号CY7C63723-PC的Datasheet PDF文件第9页  
    FOR
    FOR
    enCoRe™
    USB CY7C63722/23
    CY7C63743
    Figure 17-4.
    Figure 18-1.
    Figure 18-2.
    Figure 18-3.
    Figure 19-1.
    Figure 19-2.
    Figure 19-3.
    Figure 19-4.
    Figure 19-5.
    Figure 19-6.
    Figure 19-7.
    Figure 20-1.
    Figure 21-1.
    Figure 21-2.
    Figure 21-3.
    Figure 21-4.
    Figure 21-5.
    Figure 21-6.
    Figure 21-7.
    Figure 21-8.
    Figure 26-1.
    Figure 26-2.
    Figure 26-3.
    Figure 26-4.
    Figure 26-5.
    Figure 26-7.
    Figure 26-6.
    Figure 26-8.
    Figure 26-9.
    SPI Data Timing .............................................................................................................. 31
    Timer LSB Register (Address 0x24) ................................................................................ 31
    Timer MSB Register (Address 0x25) ............................................................................... 32
    Timer Block Diagram ....................................................................................................... 32
    Capture Timers Block Diagram ....................................................................................... 33
    Capture Timer A-Rising, Data Register (Address 0x40) ................................................. 33
    Capture Timer A-Falling, Data Register (Address 0x41) ................................................. 34
    Capture Timer B-Rising, Data Register (Address 0x42) ................................................. 34
    Capture Timer B-Falling, Data Register (Address 0x43) ................................................. 34
    Capture Timer Status Register (Address 0x45) .............................................................. 34
    Capture Timer Configuration Register (Address 0x44) ................................................... 34
    Processor Status and Control Register (Address 0xFF) ................................................. 35
    Global Interrupt Enable Register (Address 0x20) ............................................................ 38
    Endpoint Interrupt Enable Register (Address 0x21) ........................................................ 39
    Interrupt Controller Logic Block Diagram ........................................................................ 40
    Port 0 Interrupt Enable Register (Address 0x04) ............................................................ 40
    Port 1 Interrupt Enable Register (Address 0x05) ............................................................ 40
    Port 0 Interrupt Polarity Register (Address 0x06) ............................................................ 41
    Port 1 Interrupt Polarity Register (Address 0x07) ............................................................ 41
    GPIO Interrupt Diagram .................................................................................................. 41
    Clock Timing .................................................................................................................... 51
    USB Data Signal Timing .................................................................................................. 51
    Receiver Jitter Tolerance ................................................................................................ 52
    Differential to EOP Transition Skew and EOP Width ...................................................... 52
    Differential Data Jitter ...................................................................................................... 52
    SPI Slave Timing, CPHA = 0 ........................................................................................... 53
    SPI Master Timing, CPHA = 0 ......................................................................................... 53
    SPI Master Timing, CPHA = 1 ......................................................................................... 54
    SPI Slave Timing, CPHA = 1 ........................................................................................... 54
    LIST OF TABLES
    Table 8-1. I/O Register Summary ........................................................................................................ 13
    Table 11-1. Wake-up Timer Adjust Settings ........................................................................................ 18
    Table 12-1. Ports 0 and 1 Output Control Truth Table ........................................................................ 21
    Table 13-1. Control Modes to Force D+/D– Outputs ........................................................................... 24
    Table 17-1. SPI Pin Assignments ........................................................................................................ 31
    Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) ................... 35
    Table 21-1. Interrupt Vector Assignments ........................................................................................... 37
    Table 22-1. USB Register Mode Encoding for Control and Non-Control Endpoints ............................ 42
    Table 22-2. Decode table for
    Table 22-3:
    “Details of Modes for Differing Traffic Conditions” ............. 44
    Table 22-3. Details of Modes for Differing Traffic Conditions .............................................................. 45
    Table 28-1. CY7C63722-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) ............ 57
    Document #: 38-08022 Rev. **
    Page 4 of 58

    IC37:专业IC行业平台

    专业IC领域供求交易平台:提供全面的IC Datasheet资料和资讯，Datasheet 1000万数据，IC品牌1000多家。

    网站导航 Datasheet资料库 电子术语 电子百科
    服务中心 常见问题 委托交易 会员服务
    关于我们 公司简介 联系我们 免责申明

    产品索引：ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789

    深圳网络警察报警平台 公共信息安全网络监察 经营性网站备案信息 不良信息举报中心 工商网监电子标识 全国公安机关备案
    服务电话： 0755-32882616 0755-32882606 0755-32882608 0755-32882607 0755-32882615 值班和投诉电话：13715251531 ©2004-2024 IC37网 版权所有：ic37.com 版权申明 公网安备44030402000606 粤ICP备13051289号-6